Semiconductor elements configured with various semiconductor materials (hereinafter also simply referred to as “elements”), such as IC using silicon semiconductor and organic EL elements using organic semiconductors, are usually produced by repeatedly foaming a matrix of multiple elements on a wafer substrate, then dicing the substrate into individual elements known as chips. In the description below, a wafer substrate having a semiconductor element formed thereon (state prior to dicing) is also referred to as “a semiconductor wafer”.
In addition to a basic element structure, various wiring structures are fabricated in a semiconductor element while in the state of a wafer, in order to add sophisticated functions and for other purposes. Such wiring structures include, for example, a redistribution layer, conductive path (through hole via) that allow the element-side face and back face to communicate with each other electrically through a wafer substrate, and the like.
As disclosed in JP-A-2000-243754, for example, an aluminum electrode (an electrode pad included in an element as a semiconductor element structure) is formed, after which an insulating layer, a Cu-plated layer and the like are sequentially formed thereon, whereby a redistribution layer is formed.
After being provided with a wiring structure and divided into chips, any element serves as a semiconductor device with a connecting conductor that facilitates connection to, and mounting of, external conductors (external circuits and the like), compared with the original element, which simply has an electrode exposed.
For example, by providing a redistribution layer, aluminum electrodes of the element and conductors on an external circuit for mounting the element can easily be connected, even if they differ from each other in size or pitch.
Connection terminals can be formed on the back face of a wafer substrate by providing through hole vias that penetrate the wafer substrate in the direction of the substrate thickness.
Through investigations of such wiring structures to be added to a semiconductor element, the present inventors found that there was a room for further improvement in the two matters shown below, and identified them as problems to be solved by the present invention.
The first matter concerns manufacturing cost relating to a redistribution layer. The present inventors took note of the fact that processing for forming a redistribution layer directly on a semiconductor wafer is painstaking because of the necessity for building a redistribution layer on each semiconductor wafer, so that there is a room for reducing the manufacturing cost, although this had not been deemed a problem. If a redistribution layer formed is found to be of unacceptable quality, and even if the semiconductor wafer obtained is of acceptable quality as a whole, disposal of the semiconductor wafer as well is unavoidable, which increases the manufacturing cost, because the redistribution layer has already been formed monolithically on the semiconductor wafer.
The second matter concerns quality when a through hole via is formed in a semiconductor wafer, to which a separately formed interposer (a kind of wiring circuit substrate interposed for chip mounting) is connected. Because a through hole via is usually formed by filling a conductive paste in a through hole, the both ends thereof can protrude from the substrate faces of the semiconductor wafer, and the heights of the protrusions are variable. If an interposer is placed between an element with such protrusions and an external conductor while connecting both, the protrusion height variation causes a small gap in the interface between the interposer and the semiconductor wafer, which in turn can cause a connection failure in some elements, and reduce the reliability of the semiconductor device.
Problems to be solved by the present invention reside in improving the above-described two matters of which the present inventors took note. It is a first purpose of the present invention to provide a manufacturing method that enables a reduction of the manufacturing cost for redistribution layers conferred to semiconductor elements. A second purpose of the present invention is to provide a manufacturing method that enables production of a gapless semiconductor device even in the presence of variation in the heights of protrusions in the ends of a through hole via.